ATMEGA169P-16MCHR【PDF 211/274 页】MCU AVR 16KB FLASH 16MHZ 64-VQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3753

207页 208页 209页 210页 [211页]212页 213页 214页 215页

8018P–AVR–08/10

ATmega169P

9.2

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator,

ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This

sleep mode basically halts clk

CPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

9.3

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI

start condition detection, Timer/Counter2, LCD Controller, and the Watchdog to continue operat-

ing (if enabled). This sleep mode basically halts clk

I/O, clkCPU, and clkFLASH, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an LCD controller interrupt, USI start condition interrupt, a Timer/Counter2 interrupt, an

SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can

wake up the MCU from ADC Noise Reduction mode.

9.4

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the

USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-

nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level

interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically

halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 61

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in ”Clock Sources” on page 31.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式